The breakdown voltage of a power MOS (metal-oxide-semiconductor) device such as a VDMOS (vertically diffused metal oxide semiconductor) transistor can range from about 30V to several hundred volts (e.g. 100V to 200V) depending on the technology used to fabricate the device. A very large amount of current flows in a DMOS device for drain voltages above the breakdown voltage. This condition is typically referred to as avalanche breakdown. Avalanche breakdown destroys power DMOS devices if left unabated.
For a bipolar transistor, the maximum operating voltage is typically limited to a value below the collector-base diode breakdown voltage (Vcbo), and above the collector-emitter breakdown voltage (Vceo) for a bipolar device with a floating base. Device instability can arise when a bipolar device is in active operation between Vceo and Vcbo. When Vice rises above a certain critical voltage, the bipolar device enters a high current state. The high-current state is driven by bipolar amplification of the impact-ionization current generated in the base-collector space-charge region of the device. In some cases, the bipolar device may go into a lateral instability or pinch-in instability where the current flow pinches into a very narrow channel at the point furthest away from the base contacts. The bipolar device may enter a vertical instability or plasma state with the base and the base-collector space-charge region flooded with carriers of both types. This state corresponds to the Vceo breakdown voltage for the switched off device. In this state and depending on the bias conditions on the base and emitter, the total current can still be limited by the device itself due to an effective reduction of the peak electrical field by the carriers flooding the base collector space charge region. Each of these high current states results in an oscillating behavior with quite high amplitudes on the emitter and base. Even if the bipolar device itself is not destroyed in this oscillating state, the oscillations pose a very serious threat to other low voltage devices in adjacent circuit blocks and should be avoided.
Because of these effects, the operating voltage of a bipolar transistor is smaller than that of a corresponding unipolar device such as a vertical DMOS constructed in the same epitaxial semiconductor layer. This limits the technology voltage of an integrated power technology which provides both power and bipolar transistors on the same die, and thus poses a severe constraint for the optimization of the technology, particularly with respect to DMOS on resistance. In essence, a trade-off must be made between a highly doped thin epitaxial layer which is favorable for power transistors and a lower doped thicker epitaxial layer which is advantageous for bipolar transistors.
Existing power technologies especially of the CMOS-DMOS type (i.e. vertical DMOS with a common drain on the substrate) must take great care to avoid triggering of parasitic substrate bipolars and control the maximum collector voltage during active operation of the parasitic substrate bipolars. Also, the minimum usable thickness of the epitaxial layer is a highly important optimization parameter for on-resistance of a DMOS device and can be limited by the parasitic substrate bipolars. For some power applications, SOI (silicon-on-insulator) technologies can be used, where devices are dielectrically isolated and thus can be more easily optimized individually. However, SOI costs more than non-SOI technologies. In advanced bipolar technologies, deep trench isolation and/or shallow trench isolation is used to terminate the bipolar device, but not as a constructive element of the core bipolar transistor. Instead, the trench structures are only used for lateral isolation and do not affect the electrical characteristics of the core bipolar transistor.